NOR Flash Interface
• NOR Flash Interface supporting generic asynchronous memory
• Customizable to Compact Flash
• Programmable Setup, Access, Hold and Transition times
• Can address up to 64 MB and 8/16-bit bus
NAND Flash Interface
• Compliant to ONFI2.2
• Compliant to AMBA AHB, APB 2.0
• Supports different formats including but not limited to Micron, Samsung, Hynix
ONFI2.2 Features
• Supports Asynchronous [0-5] and Synchronous [0-5] mode of operation
• Supports Interleaved read Operations
• Supports Interleaved Page Program and Erase Operations
• Supports Multiple LUN Operations
• Supports all mandatory commands and most of the optional commands
• Complete Access to Spare Area
Data Interface and Timing
• Supports all Asynchronous modes[0-5]
• Supports all Synchronous modes[0-5]
• 8 bit Data Bus Width
• Highly Configurable for command and data cycles
Configuration
• Programmable page size – 512B, 2KB, 4KB, 8KB, 16KB
• Configurable FIFO Depth - typical (256 x 32)
• Support ECC Enable and Disable Option
• Programmable Access Timing
Error Correction Codes (ECC)
• Supports Hamming Code (1 bit error correction and 2 bit error detection)
• Supports BCH Code (up to 40 bit error correction)
Boot Mode
• Customizable boot options
• DMA for boot code transfer
• Boot from NAND/SRAM/SPI-supported
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Serial Flash Interface
• SPI Master Interface at 50 MHz
• Master Clock derived from the AHB (System) Clock
• Supports mode0, mode3
• Programmable CPOL, CPHA
• Individually Controllable pins to drive chip-select, write protect and hold signals
• System Interface at 50-200 MHz
Slave Interface
• Configurable Command/Data buffer
• The IP can be configured to have 4 to 16 Command/Data buffers
• Thresholds to generate interrupts
• Configurable AHB/APB bus.
• Control and Status Registers to configure the modules
• System Interface at 50-200 MHz
• Programmed IO Mode (PIO) Data Transfer
Master Interface
• Supports Advanced High Performance Bus (AHB)
• Supports Single, INCR4, INCR8, INCR16 Burst mode of Operation
• Supports all slave device responses
• DMA used for Boot Code and Data transfer
Block Level Design Features
• Supports Advanced Single Clock based design. Slow frequency clocks derived from master clock Performance Bus (AHB)
