Posedge-SUBSYS-1.1 - Processor Independent AHB-APB subsystem

Processor Independent AHB-APB sub-system IP is a highly configurable set of basic peripherals required to implement an SoC.

The System Components are glued together with a fully compliant AHB interface. (AXI in development now)

Features

• AMBA AHB 2.0 Protocol Compliant Master/Slave Interfaces
• AMBA AHB 2.0 Protocol Compliant Arbiter
• 16550 buffered UART
• 50 MHz Serial Flash Controller
• SPI Master/Slave Controller
• I2C Master/Slave Controller
• General Purpose Timer
• General Purpose I/O
• GP DMA with direct connectivity to hardware peripherals
• Very low latency DDR-I/DDR-II Controller (up to 533 MHz)

Benefits

• The designs are verified in Silicon, in FPGA and using third party verification IP
• The design blocks are fully compliant with the respective protocols

Deliverables

• Fully Synthesizable RTL
• Testbenches and Testcases
• ASIC Synthesis Scripts
• FPGA Synthesis and P&R Scripts
• Documentation

Tech Specs

Part Number	Posedge-SUBSYS-1.1
Short description	Processor Independent AHB-APB subsystem
Provider:	Posedge Inc
Portability	ASIC, FPGA
Type	Soft
Maturity	Available in FPGA platform and Proven in Silicon
Availability	Now
FPGA Technology:	Xilinx: Virtex-4 LX