Posedge AES Crypto Engine

Overview

Posedge AES Crypto Engine IP is a Silicon-proven high performance crypto core. The core is flexible and can be configured for various data rates and sizes depending on the application. The design supports EBC, CBC, and CTR modes of operation and is used in variety of applications including high end security devices implementing IPSEC. The AES crypto engine provides a simple interface for data and keys to easily integrate with the rest of the system. The design operates at 300 MHz in 90nm and delivers 128-bit blocks per 12 cycles (3.2 Gbps) with 70K gates. The optimized design for gate count is 30k and achieves a throughput of 1 Gbps. The block performs both encryption and decryption. The base design can be configured to run at lower clock speeds by loop unrolling (with more area). The design is amenable to be implemented using T-Boxes and pre-computed Round Key Memory for higher throughput.

Features

AES Crypto Engine:
• AES Crypto Engine Compliant with FIPS 197 NIST publication
• Supports OFB, CFB, CCM, CBC, CTR, and EBC modes
• Supports 128, 192, and 256-bit keys
• Encryption and Decryption using the same block
• 70K gates at 300 MHz in 90nm technology. (30K gates for area optimized)
• 3.2 Gbps performance for 128 bit Key length
• Silicon and FPGA Proven and is interoperated with IPSEC devices
• Automatic Round Key generation per cycle

Slave Interface:
• Zero dead cycle operation
• Optional memory for Round Keys
• Configurable to connect to APB or AHB or a MIPS style Co-Processor bus
• Customizable to add a staging layer for key and data storage

Block Level Design:
• Single Clock based design
• Fully scan-able

Benefits

• Flexible enough to configure various data rates and sizes depending on the applications
• Supports EBC, CBC and CTR modes of operation
• Provides simple interface for integration
• Performs both encryption and decryption

Deliverables

• Fully Synthesizable Verilog RTL
• Architecture Specification
• Self-checking Testbench and Testcases
• ASIC/FPGA Synthesis Scripts
• Integration Manual
• Software Drivers

Tech Specs

Part Number	Posedge-AES
Short description	Posedge-AES engine
Provider:	Posedge Inc
Portability	ASIC, FPGA, Structured ASIC
Type	Soft
Maturity	FPGA Implementation
Availability	Now
FPGA Technology:	Xilinx: Virtex-5 LX