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Posedge ONFI3.0 Universal Flash Controller
ONFI3.0 Universal Flash Controller (PE-UFC 3.0) IP provides an interface to NAND, NOR, SRAM and Serial flash devices. The UFC has an AXI/AHB/APB (configurable – default AHB) slave interface to connect to the SoC. The data from the external devices (Flash or Serial peripheral) can be transferred using register I/O – Programmed IO Mode (PIO) or using DMA mode. The UFC can work up to 80 MHz of serial interface and up to 400 MHz on the NAND interface. To ensure less overhead for the Host processor controlling the data transfers, multiple commands can be queued. The Controller can queue up to 32 commands and will have 1024 byte deep data buffers for data transfer. The UFC is designed to meet timing very easily at all the interfaces. |
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ONFI3.0 Universal Flash Controller |
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Features |
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• Supports NAND/NOR/SRAM/SPI Interface
• Compliant to ONFI3.0 Specification
• Compliant to AMBA AHB 2.0, APB 3.0, AXI 2.0
• Error Correction (Upto 40 bits)
• Programmable Page size (Upto 16K)
• Programmable Code Size (512B/1KB)
• DMA mode for Fast Data Rate Transfer
• Programmable Access Timing
• Supports SLC and MLC Flash Devices
• Supports up to 8 Banks
• Supports single, INCR4, INCR8, and INCR16 Burst mode of operation
• Supports all slave device responses
• Configurable Command/Data buffer
• Thresholds to generate interrupts
• Configurable to be AHB/APB/AXI bus
• Programmable Tap Delay Logic
• Data Transfer Modes
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Nand Flash Controller |
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Compliance |
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• Compliant to ONFI3.0, AMBA AHB, APB2.0, AXI |
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• Supports different formats such as Micron, Samsung, Hynix |
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ONFI3.0 Features |
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• Supports SDR modes (0-5), NV-DDR modes (0-5) and NV-DDR-2 modes (0-7) |
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• Interleaved page program / read and erase operations |
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• Multiple LUN / plane operations |
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• All mandatory commands and optional command are supported |
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• Warm up cycles for data input and data output |
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• Complete access to spare area |
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• 8bit/16bit Data Bus width |
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Configuration |
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• Programmable page size - 512B, 2KB, 4KB, 8KB, 16KB |
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• Supports ECC enable and disable options |
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• Programmable access timing |
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• Programmable Row (1-4Bytes) and Col Address Cycles (1-4Bytes) |
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Error Correction (ECC) |
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• Supports Hamming Code (1 bit error correction and 2 bit error detection) |
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• Supports BCH Code (Upto 40bit error correction) |
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• Programmable code word size for ECC (512 bytes to 1024 bytes) |
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NOR/SRAM Flash Interface |
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• Supports Generic Asynchronous and Synchronous Interface |
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• Supports Multiplex and non-multiplex mode |
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• Supports Programmable setup, access, hold, and transition times |
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• Supports 8/16/32 bit bus |
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• Supports Burst and Non-Burst Devices |
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• Programmable Address Mapping |
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Serial Flash Interface |
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• SPI master interface at 80 MHz |
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• Programmable CPOL, CPHA |
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• Individually controllable pins used to drive chip-select, write protect, and hold signals |
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• Supports Boot/XIP mode |
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• Supports single/dual/quad mode. |
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>> Back |
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United States |
India - Hyderabad |
India - Bangalore |
Taiwan |
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2901 Tasman Dr, Suite 113,
Santa Clara, CA - 95054
Tel : +1 408-385-7680
Fax : +1 408-872-4206 |
Unit - 2, 5th Floor, Building No 9,
Mindspace, Hitech City,
Madhapur, Hyderabad,
Andhra Pradesh - 500 081
Tel : +91 40 44182299
Fax : +91 40 4418 2235 |
1st Floor,
No.7/3,
Old Madras Road,
Opp: 100ft Road, Indiranagar,
Bangalore - 560038
Tel : +91 080 42028553, 25304488 |
11F, No. 206, Sec. 1,
Fu-Xing S. Rd. Taipei, Taiwan |
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| © 2013 Posedge. All Rights Reserved. |
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